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Performance Limits of the Self‐Aligned Nanowire Top‐Gated MoS 2 Transistors
Author(s) -
Yang Zhenyu,
Liu Xingqiang,
Zou Xuming,
Wang Jingli,
Ma Chao,
Jiang Changzhong,
Ho Johnny C.,
Pan Caofeng,
Xiao Xiangheng,
Xiong Jie,
Liao Lei
Publication year - 2017
Publication title -
advanced functional materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 6.069
H-Index - 322
eISSN - 1616-3028
pISSN - 1616-301X
DOI - 10.1002/adfm.201602250
Subject(s) - materials science , nanowire , optoelectronics , transistor , subthreshold slope , scattering , field effect transistor , dielectric , phonon scattering , nanotechnology , electrical engineering , optics , voltage , thermal conductivity , physics , composite material , engineering
In order to realize the promising potential of MoS 2 as the alternative channel material, it is essential to achieve high‐performance top‐gated MoS 2 field‐effect transistors (FETs), especially since the back‐gated counterparts cannot control the device individually. Although uniform high‐ k dielectric films, such as HfO 2 , can be obtained through the introduction of artificial nucleation sites on the MoS 2 channel to fabricate top‐gated FETs, this would inevitably degrade their channel/dielectric interface quality, induce significant charged impurity scattering and lower carrier mobility. In this work, MoS 2 FETs are fabricated using a self‐aligned nanowire top‐gate, which can effectively reduce the charged impurity scattering on the surface of MoS 2 . Specifically, the fabricated short‐channel devices exhibit impressive electrical performances, such as the high on/off current ratio, low interface trap density, and near‐ideal subthreshold slope at room temperature. In addition, the short channel effect is systematically analyzed, which indicates that the phonon scattering can be the dominant scattering mechanism in the devices when the amount of charged impurities is effectively reduced with the self‐aligned nanowire gate. All these provide an enhanced fabrication scheme to attain top‐gated short‐channel devices with the optimized interface and potentially to explore their corresponding performance limits.