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Parallel architectures for RLS with directional forgetting
Author(s) -
Chisci L.,
Mosca E.
Publication year - 1987
Publication title -
international journal of adaptive control and signal processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.73
H-Index - 66
eISSN - 1099-1115
pISSN - 0890-6327
DOI - 10.1002/acs.4480010106
Subject(s) - forgetting , throughput , computer science , parallel computing , recursive least squares filter , algorithm , telecommunications , wireless , adaptive filter , linguistics , philosophy
Abstract Efficient parallel architectures for recursive least squares with directional forgetting are presented. Two different arrays are proposed. The first employs O(n) processors and exhibits a 1/(2 n + 3) throughput rate, n being the number of parameters to be estimated. The second can achieve a 1/( n + 2) throughput rate at the expense of an O(n 2 ) processor complexity. Both architectures make use of the UD algorithm, here properly modified so as to embody the directional‐forgetting variant.