Open AccessHigh‐voltage DC circuit breaker with gradual fault‐current limitation mechanism for VSC‐HVDC applications
Author(s) -
Ahmad Muhammad,
Wang Zhixin,
Zhang Yong
Publication year - 2020
Publication title -
international transactions on electrical energy systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.428
H-Index - 42
ISSN - 2050-7038
DOI - 10.1002/2050-7038.12468
Subject(s) - circuit breaker , fault current limiter , current limiting , transient recovery voltage , fault (geology) , engineering , electrical engineering , inductor , voltage , electronic engineering , voltage source , electric power system , physics , power (physics) , seismology , geology , quantum mechanics , dropout voltage
Summary Fault‐current limiters are generally deployed to overcome the capacity issues of high‐voltage direct current circuit breakers. This research work reports a hybrid direct current circuit breaker with an incremental fault‐current limiting circuit, in order to protect high‐voltage direct current transmission lines based on voltage source converters, against commonly appearing line‐to‐line or line‐to‐ground faults. The proposed breaker comprises of three branches: branch for the normal current flow, high inductance carrying branch for the fault‐current limitation, and branch to isolate the fault current. The normal current carrying path contains a bidirectional switch, breaker impedance, and a mechanical disconnector. Incremental fault‐current limiting circuit is placed in fault‐current limiting branch, which consists of n ‐numbers of branches in a parallel configuration, and each branch is composed of a bidirectional switch and a current limiting inductor. By the application of incremental fault‐current limiting circuit, the fault current is decreased gradually; at the terminal stage the residual current is transferred to fault‐current isolation branch, which is composed of metal oxide arrester. The article further includes a detailed working principle of the proposed breaker, an analytical model for fault‐current estimation, and criteria to optimize the size of current limiting inductors in incremental fault‐current limiting circuit. The theoretical analysis is verified using equivalent circuit approach and three‐terminal voltage source converter based direct current transmission line model. PSCAD/EMTDC software is used to acquire the simulation results. The performance of the proposed breaker is equated with some of the existing topologies, for rigorous comparative analysis to gauge the competitiveness.