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FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems
Author(s) -
Quan Zhi,
Zakharov Yuriy
Publication year - 2016
Publication title -
radio science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.371
H-Index - 84
eISSN - 1944-799X
pISSN - 0048-6604
DOI - 10.1002/2016rs006021
Subject(s) - detector , field programmable gate array , computer science , mimo , minimum mean square error , convergence (economics) , gate array , coordinate descent , computer hardware , algorithm , mathematics , telecommunications , channel (broadcasting) , statistics , estimator , economics , economic growth
This paper proposes an improved architecture of a low‐complexity box‐constrained multiple‐input multiple‐output (MIMO) detector which is based on the dichotomous coordinate descent (DCD) algorithm. This architecture allows a simple field‐programmable gate‐array implementation of the detector and explores the parallel implementation to reduce the number of clock cycles required in the design. We investigate the proposed design and compare its detection performance, hardware resources, and convergence speed with that of known designs. It is shown that the proposed design provides improvement in the detection performance compared to the minimum mean square error (MMSE) detector. The numerical results also show that the proposed architecture requires as few as 184, 210, and 223 slices for 16 × 16, 64 × 64, and 128 × 128 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector. By comparing the serial and parallel implementations of the box‐constrained detector, we show that the parallel implementation requires 15% fewer clock cycles.