A parallel unbalanced digitization architecture to reduce the dynamic range of multiple signals

Technologies employed in urban sensor networks are permanently evolving, and thus the gateways employed to collect data in such kind of networks have to be very flexible in order to be compliant with the new communication standards. A convenient way to do that is to digitize all the received signals in one shot and then to digitally perform the signal processing, as it is done in software‐defined radio (SDR). All signals can be emitted with very different features (bandwidth, modulation type, and power level) in order to respond to the various propagation conditions. Their difference in terms of power levels is a problem when digitizing them together, as no current commercial analog‐to‐digital converter (ADC) can provide a fine enough resolution to digitize this high dynamic range between the weakest possible signal in the presence of a stronger signal. This paper presents an RF front end receiver architecture capable of handling this problem by using two ADCs of lower resolutions. The architecture is validated through a set of simulations using Keysight's ADS software. The main validation criterion is the bit error rate comparison with a classical receiver.