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Simulation of Single‐Electron Tunneling Circuits
Author(s) -
Gerousis C.P.,
Goodnick S.M.
Publication year - 2002
Publication title -
physica status solidi (b)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.51
H-Index - 109
eISSN - 1521-3951
pISSN - 0370-1972
DOI - 10.1002/1521-3951(200209)233:1<113::aid-pssb113>3.0.co;2-a
Subject(s) - nanodevice , computer science , cmos , topology (electrical circuits) , node (physics) , electronic circuit , electronic engineering , set (abstract data type) , inverter , transistor , power (physics) , computer engineering , electrical engineering , physics , engineering , nanotechnology , materials science , quantum mechanics , voltage , programming language
We investigate the use of nanoelectronic structures in cellular non‐linear network (CNN) architectures, for potential application in future high density and low power CMOS‐nanodevice hybrid circuits. We first review the operation of the single‐electron tunneling (SET) transistor to be used in analog processing arrays for image processing applications. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non‐linear transfer characteristics for individual cells. The basic SET‐CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN‐like behavior in attempting to realize different functionality such as shadowing. Finally, we discuss the speed and signal delay in SET networks, and estimate the power consumption of the SET‐CNN and compare it to a state‐of‐the‐art CMOS processor.