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Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine
Author(s) -
Uzsoy Reha,
Lee ChungYee,
MartinVega Louis A.
Publication year - 1992
Publication title -
naval research logistics (nrl)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.665
H-Index - 68
eISSN - 1520-6750
pISSN - 0894-069X
DOI - 10.1002/1520-6750(199204)39:3<369::aid-nav3220390307>3.0.co;2-f
Subject(s) - scheduling (production processes) , computer science , single machine scheduling , due date , test (biology) , operations management , mathematical optimization , job shop scheduling , mathematics , engineering , operating system , schedule , paleontology , biology
We examine a class of single‐machine scheduling problems with sequence‐dependent setup times that arise in the context of semiconductor test operations. We present heuristics for the problems of minimizing maximum lateness with dynamic arrivals and minimizing number of tardy jobs. We exploit special problem structure to derive worst‐case error bounds. The special problem structure also enables us to derive dynamic programming procedures for the problems where all jobs are available simultaneously.