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Toward nanoelectronic cellular neural networks
Author(s) -
Gerousis C.,
Goodnick S. M.,
Porod W.
Publication year - 2000
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/1097-007x(200011/12)28:6<523::aid-cta125>3.0.co;2-r
Subject(s) - nanodevice , cmos , computer science , topology (electrical circuits) , node (physics) , set (abstract data type) , electronic circuit , electronic engineering , spice , inverter , transistor , electrical engineering , engineering , nanotechnology , materials science , voltage , structural engineering , programming language
We investigate the use of nanoelectronic structures in cellular non‐linear network (CNN) architectures, for potential application in future high‐density and low‐power CMOS‐nanodevice hybrid circuits. We first investigate compact models for simulation of single‐electron tunnelling (SET) transistors appropriate for use in coupled SET–CMOS circuits. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non‐linear transfer characteristic of individual cells. This basic SET CNN cell acts as a summing node, which is capacitively coupled to the inputs and outputs of nearest neighbour cells. Monte Carlo simulation results are then used to show CNN‐like behaviour in attempting to realize different functionality such as a connected component detector and shadowing. Copyright © 2000 John Wiley & Sons, Ltd.