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A neural network parallel algorithm for one‐dimensional gate assignment problems
Author(s) -
Tsuchiya Kazuhiro,
Takefuji Yoshiyasu,
Kurotani Kenichi
Publication year - 1999
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/(sici)1520-6416(19991115)129:2<71::aid-eej8>3.0.co;2-d
Subject(s) - very large scale integration , benchmark (surveying) , artificial neural network , folding (dsp implementation) , computer science , algorithm , parallel computing , engineering , artificial intelligence , embedded system , electrical engineering , geodesy , geography
A near‐optimum parallel algorithm for solving the one‐dimensional gate assignment problem is presented in this paper, where the problem is NP‐hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n × n processing elements based on the artificial two‐dimensional maximum neural network for (n + 2)‐gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem. © 1999 Scripta Technica, Electr Eng Jpn, 129(2): 71–77, 1999