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Transformation algorithm from Ladder Diagram to SFC using temporal logic
Author(s) -
Zanma Tadanao,
Suzuki Tatsuya,
Inaba Akio,
Okuma Shigeru
Publication year - 1999
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/(sici)1520-6416(199910)129:1<74::aid-eej9>3.0.co;2-b
Subject(s) - transformation (genetics) , ladder logic , algorithm , diagram , computer science , programmable logic controller , chemistry , biochemistry , database , gene , operating system
The Ladder Diagram (LD) has been widely used in industry as a language for sequential control. However, the LD cannot represent sequential flows of control logic explicitly. This leads to difficulties for other engineers in understanding the control logic. To overcome this problem, the Sequential Function Chart (SFC) has been proposed. Because the SFC can represent sequential flow explicitly, it is expected to be used more widely. Since the LD has been widely used in the past, however, it is necessary to develop an algorithm for transformation from the LD to the SFC. In this paper, a technique to transform an LD to the corresponding SFC by using temporal logic is proposed. In the closed loop system which consists of the LD and the controlled plant, sequence information including parallel path divergences is extracted to develop the transformation algorithm. An example is presented to verify the feasibility of the proposed algorithm. © 1999 Scripta Technica, Electr Eng Jpn, 129(1): 74–81, 1999