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Implementation of Petri nets using a field‐programmable gate array
Author(s) -
Yang S. K.,
Liu T. S.
Publication year - 2000
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/(sici)1099-1638(200003/04)16:2<99::aid-qre308>3.0.co;2-j
Subject(s) - petri net , field programmable gate array , application specific integrated circuit , computer science , gate array , process architecture , petri dish , embedded system , programmable logic device , function (biology) , field (mathematics) , computer hardware , distributed computing , mathematics , biology , pure mathematics , genetics , evolutionary biology
Although Petri nets have various capabilities, the Petri net approach is done on paper. A field‐programmable gate array (FPGA) is implemented in this study so as to realize basic Petri net symbols, logic structures in Petri nets, and specific functions for Petri nets by logic circuits. As an example, a Petri net for an early failure detection and isolation arrangement (EFDIA) is implemented as an application‐specific integrated circuit (ASIC) on a Xilinx Demonstration Board. This ASIC is verified by three simulations dealing with three different failure scenarios of a system, and the ASIC functions identically to the EFDIA Petri net. Accordingly, not only the EFDIA Petri net but also any specific function Petri nets can be implemented by FPGA circuits. Copyright © 2000 John Wiley & Sons, Ltd.