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Process monitoring in integrated circuit fabrication using both yield and spatial statistics
Author(s) -
Collica Randall S.,
Ramírez José G.,
Taam Winson
Publication year - 1996
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/(sici)1099-1638(199605)12:3<195::aid-qre8>3.0.co;2-z
Subject(s) - integrated circuit , yield (engineering) , process (computing) , statistics , semiconductor device fabrication , computer science , electronic circuit , data mining , engineering , mathematics , electrical engineering , materials science , wafer , metallurgy , operating system
This paper presents the charting of spatial statistics in addition to yield information from the integrated circuits fabrication processes to detect systematic patterns. Early detection of process anomalies is critical for the manufacturing of integrated circuits because of its long cycle time. Charting spatial statistics provides opportunities to detect special causes that go undetected using only yield statistics. Examples from IC manufacturing processes are used to demonstrate this method.