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Modelling and estimation of wafer yields and defect densities from microelectronics test structure data
Author(s) -
Hansen Christian K.,
Thyregod Poul
Publication year - 1996
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/(sici)1099-1638(199601)12:1<9::aid-qre975>3.0.co;2-k
Subject(s) - very large scale integration , microelectronics , wafer , outlier , engineering , test data , integrated circuit , computer science , reliability engineering , electronic engineering , data mining , artificial intelligence , electrical engineering , software engineering
Test structures are being used widely in microchip manufacturing in order to extract yield information for VLSI circuits manufactured in the same technology. We present and discuss a statistical method used for predicting full scale wafer yields, based on an ‘outlier detection’ principle applied to scaled test structure electrical and visual data. A case study, based on data from a joint ALCATEL ESPACE/INTELSAT research project, illustrates a successful application of this methodology.