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The design of a block‐regularized parameter estimator by algorithmic engineering
Author(s) -
Brown D. W.,
McWhirter J. G.
Publication year - 1997
Publication title -
international journal of adaptive control and signal processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.73
H-Index - 66
eISSN - 1099-1115
pISSN - 0890-6327
DOI - 10.1002/(sici)1099-1115(199708)11:5<381::aid-acs414>3.0.co;2-x
Subject(s) - estimator , signal flow graph , regularization (linguistics) , algorithm , block (permutation group theory) , computation , representation (politics) , computer science , estimation theory , simple (philosophy) , least squares function approximation , flow (mathematics) , mathematical optimization , signal processing , mathematics , artificial intelligence , engineering , statistics , philosophy , geometry , electrical engineering , epistemology , politics , law , political science , telecommunications , radar
Abstract Hierarchical signal flow graphs (HSFGs) are used to illustrate the computations and data flow required for the block‐regularized parameter estimation algorithm. Block regularization protects the underlying recursive least squares (RLS) parameter estimation from numerical difficulties which can occur if the input data are not persistently exciting or the behaviour of the underlying model is unknown. Hierarchical signal flow graphs provide a very concise representation of the algorithm and a relatively simple approach to the design of efficient parallel architectures. The design of a two‐dimensional systolic array is demonstrated in the paper. © 1997 John Wiley & Sons, Ltd.