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Generic VLSI architecture for block‐matching motion estimation algorithms
Author(s) -
He Zhong L.,
Liou Ming L.,
Chan Philip. C. H.,
Tsui C. Y.
Publication year - 1998
Publication title -
international journal of imaging systems and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.359
H-Index - 47
eISSN - 1098-1098
pISSN - 0899-9457
DOI - 10.1002/(sici)1098-1098(1998)9:4<257::aid-ima8>3.0.co;2-9
Subject(s) - computer science , very large scale integration , motion vector , motion estimation , block (permutation group theory) , algorithm , scalability , matching (statistics) , architecture , dependency (uml) , quarter pixel motion , parallel computing , computer engineering , computer architecture , theoretical computer science , artificial intelligence , embedded system , mathematics , art , visual arts , statistics , geometry , database , image (mathematics)
In this article, a generic VLSI architecture which is both programmable and scalable is proposed for block‐matching motion estimation algorithms. Various motion estimation algorithms can be implemented using the proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processed in parallel by fully exploiting its data dependency. The optimal choice for the size of checking vector is discussed based on the design tradeoffs among processing speed, silicon area, and I/O bandwidth. Appropriate designs are recommended for various video applications. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol, 9, 257–273, 1998