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On the representation of static hysteresis curves by a PWL ladder circuit
Author(s) -
Storace Marco,
Parodi Mauro
Publication year - 1998
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/(sici)1097-007x(199803/04)26:2<167::aid-cta988>3.0.co;2-d
Subject(s) - piecewise linear function , capacitor , resistor , representation (politics) , hysteresis , mathematics , control theory (sociology) , scalar (mathematics) , piecewise , topology (electrical circuits) , computer science , voltage , mathematical analysis , engineering , physics , electrical engineering , geometry , control (management) , quantum mechanics , artificial intelligence , combinatorics , politics , political science , law
Abstract Some important features of static hysteretic phenomena can be suitably represented by a recently proposed ladder circuit model. The elementary cell of this ladder is constituted by a linear capacitor and a non‐linear resistor with a proper piecewise linear (PWL) characteristic. With respect to the original formulation, the representation capabilities of the model can be improved by introducing proper generalizations. These generalizations concern the definition of the hysteretic (output) variable and the initial states of the circuit capacitors. After introducing these concepts, this paper addresses the determination of the model parameters that give the best fit of the experimental data of a scalar rate‐independent hysteresis. The solution of this identification problem is obtained both for a limit cycle and for a cycle together with its first polarization curve. © 1998 John Wiley & Sons, Ltd.