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Using CAD tools for shortening the design cycle of high‐performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
Author(s) -
Medeiro Fernando,
PérezVerdú Belén,
De La Rosa José M.,
RodríguezVázquez Ángel
Publication year - 1997
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/(sici)1097-007x(199709/10)25:5<319::aid-cta976>3.0.co;2-u
Subject(s) - cmos , application specific integrated circuit , delta sigma modulation , electronic engineering , cad , power (physics) , power consumption , engineering , die (integrated circuit) , electrical engineering , 16 bit , physics , engineering drawing , mechanical engineering , quantum mechanics
This paper uses a CAD methodology proposed by the authors to design a low‐power second‐order ΣΔM. This modulator has been fabricated in a 0·7 μm CMOS technology to be used as the front‐end of an energy‐metering mixed‐signal ASIC and features 16·4 bit at a digital output rate of 9·6 kHz with a power consumption of 1·71 mW. It yields a value of the power(W)/(2 Resolution(bit) ×output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high‐performance embeddable ΣΔMs using CAD methodologies. © 1997 by John Wiley & Sons, Ltd.