Systolic digital filters with reduced latency—serial implementation

Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bit‐serial or digit‐serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow‐graph appropriate for bit‐serial or digit‐serial arithmetic is presented. Next we show how the resulting flow‐graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow‐graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two‐way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two‐way pipeline structure. In order to maintain the data word rate, the full‐bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit‐serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low‐latency high‐throughput systolic arrays for FIR and IIR digital filters. These schemes for bit‐serial multipliers and filters are also extended to digit‐serial arithmetic.