Method for Suppressing Gate Voltage Oscillations in Magnetically Coupled Gate Drives for Series‐Connected Power Semiconductor Devices

ABSTRACT This study examines the gate magnetic coupling technique, a gate drive technology for series‐connected power semiconductor devices, and discusses the generation principle of gate voltage oscillation specific to the technique and its countermeasures. Additionally, this study proposes two gate‐drive circuits designed to suppress gate voltage oscillation. The experimental results obtained using 3.3 kV/750 A SiC‐MOSFET/SiC‐SBD power modules demonstrate that the proposed methods can suppress gate voltage oscillation and reduce the voltage imbalance between the series‐connected elements.