z-logo
open-access-imgOpen Access
Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators
Author(s) -
Christophe Alias,
Alain Darte,
Alexandru Plesco
Publication year - 2010
Publication title -
hal (le centre pour la communication scientifique directe)
Language(s) - Uncategorized
Resource type - Conference proceedings
Subject(s) - computer science , compiler , interfacing , vhdl , embedded system , high level synthesis , computer architecture , field programmable gate array , code generation , memory bandwidth , verilog , computer hardware , operating system , key (lock)

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here