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-Power, area, timing these three characteristics are very important in the design of low power VLSI systems, especially in the multimedia applications and portable devices like hearing aids, mobiles, personal digital assistants are running with battery. In the early complex designs, to achieve power and area a conventional codec design has become a major problem in the portable device which consumes more amount power and larger area. One of the mode to take this power and area problem in the portable applications is to design very optimized low power, area, a novel CODEC Design implemented using the bus Berger inverter codec specially for running with battery based portable devices. This paper suggests a CODEC system of the Berger-invert codes and a new system of encoding/decoding circuitry (a codec). Physical layout execution results prove that the new optimization design reduces the codec area and power consumption respectively by up to 15% and 33% for different bus widths. Simulations and synthesis are carried out from different tools to select the vital design factors are presented. Accordingly, to measure critical specifications of the CODEC circuit, Two variations of digital coding, encoding & decoding circuit with many transistors are fabricated. The measurement results bring out the different low power and area possibilities as well as the developed a sophisticated digital Verilog description language for encoding decoding advanced design for the object applications. The useable SOC Encounter tools offer optimized physical layout design fabricated with 65nm and 45nm technology with comparison for CODEC with limited power, area and timing which will useful for the portable devices. Keywords--CODEC, Berger Invert Code, SOC Encounter Tool, Synthesis, Digital Physical Layout.

Digital Implementation of Efficient Low-Power and Compact Codec System for Portable Devices Using CADENCE Tool