Performance Comparison of Binary LDPC Decoders and FPGA Implementation of Encoder | Zendy

Jayashree C. Nidagundi | Zendy; Siddarama R. Patil | Zendy

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Performance Comparison of Binary LDPC Decoders and FPGA Implementation of Encoder

Author(s) -

Jayashree C. Nidagundi,

Siddarama R. Patil

Publication year - 2016

Publication title -

bonfring international journal of research in communication engineering

Language(s) - English

Resource type - Journals

eISSN - 2277-5080

pISSN - 2250-110X

DOI - 10.9756/bijrce.8203

Subject(s) - low density parity check code , encoder , field programmable gate array , computer science , binary number , decoding methods , forward error correction , parallel computing , computer hardware , arithmetic , algorithm , mathematics , operating system

-Modern Communication standards deals with high and efficient data transmission and reception. LDPC codes show the error correction performance very close to Shannon’s limit. The proposed work deals with performance analysis of both hard and soft decoding methods of LDPC codes and FPGA implementation of encoder and hard decision decoding. Soft decision decoders shows very good performance for rate 1⁄2 (8,4) codes.

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