Lead Scratch Resolution through Wirebonding Process Optimization on QFN Packages | Zendy

Jonathan C. Pulido | Zendy; Frederick Ray I. Gomez | Zendy; Edwin M. Graycochea | Zendy

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Lead Scratch Resolution through Wirebonding Process Optimization on QFN Packages

Author(s) -

Jonathan C. Pulido,

Frederick Ray I. Gomez,

Edwin M. Graycochea

Publication year - 2020

Publication title -

journal of engineering research and reports

Language(s) - English

Resource type - Journals

ISSN - 2582-2926

DOI - 10.9734/jerr/2020/v15i117136

Subject(s) - quad flat no leads package , scratch , wire bonding , integrated circuit packaging , process (computing) , semiconductor device fabrication , die (integrated circuit) , computer science , manufacturing engineering , engineering , materials science , mechanical engineering , integrated circuit , nanotechnology , layer (electronics) , electrical engineering , adhesive , telecommunications , operating system , chip , wafer

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents an improvement done in quad-flat noleads (QFN) leadframe package to resolve the quantity of unit rejection due to leads scratch underneath the leadframe. Moreover, the reject manifestation was captured after wirebonding process. Parameter optimization particularly for the second bond with the combination of bond force and bond scrubbing parameters was done to totally eliminate this type of issue after wirebonding process. With the wirebonding process optimization and improvement done, a reduction of 95 percent of leads scratch occurrence was achieved.

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