Open AccessIncorporating Package Grinding Process for QFN Thin Device Manufacturing
Author(s) -
Rennier S. Rodriguez,
Frederick Ray I. Gomez
Publication year - 2020
Publication title -
journal of engineering research and reports
Language(s) - English
Resource type - Journals
ISSN - 2582-2926
DOI - 10.9734/jerr/2019/v9i217014
Subject(s) - quad flat no leads package , grinding , miniaturization , chip scale package , semiconductor device fabrication , integrated circuit packaging , process (computing) , manufacturing engineering , computer science , mechanical engineering , materials science , engineering drawing , engineering , chip , optoelectronics , nanotechnology , electrical engineering , layer (electronics) , operating system , adhesive , wafer
Package thinning, down-scaling, and miniaturization are common interests among semiconductor industries, with each manufacturing site having different approach and technical directions in providing novelties in their products. The paper offers an innovative design of manufacturing flow to reduce the semiconductor package height of a Quad-Flat No-leads (QFN) device through the application of a specialized package grinding process. The process would significantly reduce the carrier thickness for the overall package height configuration of QFN. Through this integration, the common assembly barriers and defects related in producing thin devices are eliminated, thus thinner version manufacturing becomes more simplified and efficient.
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom