A 10 Bit All-Parallel A/D Converter | Zendy

Michihiro Inoue | Zendy; T. Takemoto | Zendy; H. Sadamatsu | Zendy; Akira Matsuzawa | Zendy; K. Aono | Zendy; Kazuhiko Tsuji | Zendy

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A 10 Bit All-Parallel A/D Converter

Author(s) -

Michihiro Inoue,

T. Takemoto,

H. Sadamatsu,

Akira Matsuzawa,

K. Aono,

Kazuhiko Tsuji

Publication year - 1983

Publication title -

japanese journal of applied physics

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.487

H-Index - 129

eISSN - 1347-4065

pISSN - 0021-4922

DOI - 10.7567/jjaps.22s1.121

Subject(s) - trimming , offset (computer science) , 12 bit , chip , voltage , electronic engineering , bit (key) , computer science , transistor , materials science , optoelectronics , physics , electrical engineering , engineering , telecommunications , computer security , cmos , programming language , operating system

This paper describes a 10 bit all-parallel analog-to-digital converter with 20 MHz conversion rate. Static accuracy was achieved by suppressing the offset voltage of pair transistors to be below 0.5 mV, and by laser trimming technology to improve nonlinearity of the dc reference voltages. In regard to dynamic accuracy, an SNR of 53 dB was observed at input signal frequencies up to 1 MHz. A 3 µm bipolar process is adopted, which integrates nearly 40,000 elements onto a 9.2×9.8 mm chip.

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