Comparison of TDC Circuit Design Method to Constant Delay Time
Author(s) -
Jin-Ho Choi
Publication year - 2010
Publication title -
journal of information and communication convergence engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.28
H-Index - 6
eISSN - 2234-8883
pISSN - 2234-8255
DOI - 10.6109/jicce.2010.8.4.461
Subject(s) - computer science , time to digital converter , reliability (semiconductor) , delay calculation , digital delay line , group delay and phase delay , electronic engineering , time constant , constant (computer programming) , process (computing) , interpolation (computer graphics) , elmore delay , signal (programming language) , electrical engineering , propagation delay , computer hardware , digital signal , digital signal processing , clock signal , engineering , telecommunications , physics , bandwidth (computing) , power (physics) , quantum mechanics , operating system , frame (networking) , programming language , jitter , computer network
This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.
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