A Review of NBTI Degradation and its Impact on the Performance of SRAM
Author(s) -
Umesh Dutta,
Mukesh Soni,
Manisha Pattanaik
Publication year - 2016
Publication title -
international journal of modern education and computer science
Language(s) - English
Resource type - Journals
eISSN - 2075-017X
pISSN - 2075-0161
DOI - 10.5815/ijmecs.2016.06.08
Subject(s) - negative bias temperature instability , static random access memory , degradation (telecommunications) , reliability (semiconductor) , computer science , reliability engineering , very large scale integration , materials science , transistor , electronic engineering , embedded system , mosfet , electrical engineering , engineering , computer hardware , power (physics) , physics , telecommunications , quantum mechanics , voltage
Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom