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— This paper proposed an algorithm for logic circuits\udverification using neural networks where a model is built to be\udtrained and tested. The proposed algorithm for combinational\udcircuits' verification is based on merging two of the well-known\udlearning algorithms for neural networks. The first one is the\udPerceptron Convergence Procedure, which is used for learning\udthe functions of the standard logic gates in order to simulate the\udwhole circuit. While the second is a modified learning algorithm\udof Back-propagation neural networks to be used for the\udverification of the hardware design. The algorithm can predict\udthe gates that cause the malfunction in the circuit design.\udThis work may be considered as a step toward building\udDistributed Computer Aided Design Environments depending\udon the parallel processing architecture, particularly in the\udNeurocomputer architecture

Coupling Perceptron Convergence Procedure with Modified Back-Propagation Techniques to Verify Combinational Circuits Design