Open AccessNoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology
Author(s) -
Xingang Ju,
Liang Yang
Publication year - 2011
Publication title -
international journal of information technology and computer science
Language(s) - English
Resource type - Journals
eISSN - 2074-9015
pISSN - 2074-9007
DOI - 10.5815/ijitcs.2011.04.08
Subject(s) - computer science , interconnection , correctness , routing (electronic design automation) , node (physics) , architecture , network topology , network on a chip , routing table , network packet , distributed computing , topology (electrical circuits) , computer network , computer architecture , parallel computing , routing protocol , algorithm , mathematics , engineering , art , structural engineering , combinatorics , visual arts
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, it introduces the basic concept and architecture of the NoC, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding, routing algorithm and node degree routing direction are designed. Thirdly, the programming and simulation of 2×4 NoC interconnection architecture are designed, and it achieves uninterrupted operation. The result shows the correctness of the interconnection architecture design. Finally, it chooses XC4VSX55-12ff1148 of vertext 4 to synthesize, the maximum frequency can up to 268 MHz, which provides foundation of subsequent research and application.
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