Design of Low Power Sequential Circuit by using Adiabatic Techniques | Zendy

Priyanka Ojha | Zendy; Charu Rana | Zendy

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Design of Low Power Sequential Circuit by using Adiabatic Techniques

Author(s) -

Priyanka Ojha,

Charu Rana

Publication year - 2015

Publication title -

international journal of intelligent systems and applications

Language(s) - English

Resource type - Journals

eISSN - 2074-9058

pISSN - 2074-904X

DOI - 10.5815/ijisa.2015.08.06

Subject(s) - adiabatic circuit , computer science , spice , adiabatic process , logic optimization , pass transistor logic , dissipation , power (physics) , logic family , pull up resistor , sequential logic , electronic engineering , cmos , logic gate , electronic circuit , logic synthesis , electrical engineering , algorithm , digital electronics , physics , quantum mechanics , engineering , thermodynamics

Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.

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