Power-Time Efficient Hybrid Adder Design Based on LP with Optimal Bit-Width Generation

This paper presents a systematic method for a hybrid adder design through allocating the optimal bit-widths and types of classical adders constituting a hybrid adder. The proposed optimization scheme considers two aspects design delay and power. It is based on a mathematical modeling of the proposed hybrid adder architecture following the principle of LP (Linear Programming). Two models, delay optimization under power constraint and power optimization under delay constraint, are introduced. Various experiments are presented to demonstrate the effectiveness and applicability of the proposed design scheme. The results indicate that the proposed scheme successfully allocates simultaneously and in a systematic way the optimal bit-widths of the sub-adders constituting a hybrid adder; providing an improvement in (power x delay) performance reaching 71.6%. The results obtained also indicate that the proposed design scheme introduces a high flexibility in making a compromise between delay and power of the adder design.