Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor | Zendy

Maede Kaviani | Zendy; Hojjat Sharifi | Zendy; Mahdi Dolatshahi | Zendy; Keivan Navi | Zendy

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Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

Author(s) -

Maede Kaviani,

Hojjat Sharifi,

Mahdi Dolatshahi,

Keivan Navi

Publication year - 2016

Publication title -

international journal of engineering and manufacturing

Language(s) - English

Resource type - Journals

eISSN - 2306-5982

pISSN - 2305-3631

DOI - 10.5815/ijem.2016.01.01

Subject(s) - bicmos , cmos , capacitor , buffer (optical fiber) , electronic circuit , node (physics) , electrical engineering , bipolar junction transistor , transistor , electronic engineering , buffer amplifier , block (permutation group theory) , engineering , integrated injection logic , decoupling capacitor , voltage , computer science , pass transistor logic , geometry , mathematics , structural engineering

BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

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