Open AccessSimulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction
Author(s) -
Kalagadda Bikshalu,
V.S.K. Reddy,
M. V. Manasa,
K. Venkateswara Rao
Publication year - 2014
Publication title -
international journal of engineering and manufacturing
Language(s) - English
Resource type - Journals
eISSN - 2306-5982
pISSN - 2305-3631
DOI - 10.5815/ijem.2014.03.02
Subject(s) - cmos , mosfet , reliability (semiconductor) , electronic engineering , spice , transistor , reduction (mathematics) , dissipation , nand gate , materials science , electronic circuit , integrated circuit , inverter , power (physics) , electrical engineering , computer science , logic gate , engineering , optoelectronics , voltage , physics , geometry , mathematics , quantum mechanics , thermodynamics
Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.
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