MOS Current Mode Logic with Capacitive Coupling | Zendy

Kirti Gupta | Zendy; Neeta Pandey | Zendy; Maneesha Gupta | Zendy

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MOS Current Mode Logic with Capacitive Coupling

Author(s) -

Kirti Gupta,

Neeta Pandey,

Maneesha Gupta

Publication year - 2012

Publication title -

isrn electronics

Language(s) - English

Resource type - Journals

ISSN - 2090-8679

DOI - 10.5402/2012/473257

Subject(s) - current mode logic , nand gate , logic gate , computer science , and or invert , pass transistor logic , capacitive coupling , electronic engineering , nor logic , nmos logic , logic family , cmos , domino logic , digital electronics , fifo (computing and electronics) , logic synthesis , electrical engineering , engineering , electronic circuit , transistor , computer hardware , voltage

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

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