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This paper presents a practical procedure for designing a Reed-Solomon encoder/decoder through the functional description using hardware descriptor language (VHDL) with the programming tool Xilinx ISE 9.2i. We propose a design that use the benefits introduced by VHDL programming, its modularity feature, and the strategy for dividing the design in less complex components to facilitate the process. In addition, the methodology of the decoder design using parallel processing has been detailed. Simulations with ModelSim XE 5.7c software were carried out in order to validate the encoder/decoder behaviour.

Diseño de un codificador y decodificador digital Reed-Solomon usando programación en VHDL