Associative Processor Arrays: Simulation and Performance Estimates for Image Processing | Zendy

A.W.G. Duller | Zendy; Andrew D. Morgan | Zendy; R. Storer | Zendy

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Associative Processor Arrays: Simulation and Performance Estimates for Image Processing

Author(s) -

A.W.G. Duller,

Andrew D. Morgan,

R. Storer

Publication year - 1987

Publication title -

citeseer x (the pennsylvania state university)

Language(s) - English

Resource type - Conference proceedings

DOI - 10.5244/c.1.18

Subject(s) - computer science , associative property , image processing , parallel computing , image (mathematics) , computer architecture , computer graphics (images) , computer hardware , arithmetic , artificial intelligence , mathematics , pure mathematics

The SCAPE chip, as an example of an associative processor array, is described; performance and algorithm details are given. The difficulties which were encountered when designing a SCAPE test-bed are stated and SCAPE is compared with a number of other image processing chips and system designs. The knowledge gained from this work is then used to suggest improvements in the design of VLSI associative processor arrays for image processing tasks. To enable optimisation of associative processor array design a functional simulator has been written and results are given for a number of image processing algorithms. The design of a language which will complement these architectures is discussed.

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