A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer

A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source Coupled Logic (SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power consumption and the operating frequency. The multiplexer design employs CMOS transistors as transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at a supply voltage of 400 mV with a bias current ranging in the order of few pA. The ON and OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V. © 2015 Elixir All rights reserved. ARTICLE INFO Article h istory: Received: 28 July 2014; Received in revised form: 19 December 2014; Accepted: 29 December 2014;