Open AccessDesign of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology
Author(s) -
Ujwala A. Belorkar,
Ladhake S.A
Publication year - 2010
Publication title -
international journal of vlsi design and communication systems
Language(s) - English
Resource type - Journals
eISSN - 0976-1357
pISSN - 0976-1527
DOI - 10.5121/vlsic.2010.1201
Subject(s) - phase locked loop , pll multibit , very large scale integration , loop (graph theory) , electronic engineering , power (physics) , delay locked loop , phase (matter) , computer science , engineering , physics , phase noise , mathematics , combinatorics , quantum mechanics
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