English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

Digital multipliers are among the maximum essential arithmetic purposeful devices. The average performance of these systems relies upon at the throughput of the multiplier. In the meantime, the negative bias temperature instability impact occurs while a pMOS transistor is underneath negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier pace. A similar phenomenon, positive bias temperature instability, happens when an nMOS transistor is underneath positive bias. Each effect degrade transistor pace and in the long term, the device may also fail due to timing violations. Therefore, it is essential to design dependable high-overall performance multipliers. In this paper, suggest an aging-aware multiplier model with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and may modify the AHL circuit to mitigate overall performance degradation this is because of the aging effect. Furthermore, the proposed structure can be applied to a Pre-Encoded NR4SD Multiplier.

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design using Verilog HDL