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Field Programmable Gate Array (FPGA) technology is the popular platform for the designing of higher speed of algorithms which are used in the field of the signal processing. There are various applications which are designed by the scientist on the FPGA platform such that digital filters, their sampling rates are more than the available digital filter DSP chip. FPGA implemented digital filter has higher flexibility, low cost than the available DSP chips. In Digital signal processing area and VLSI technology there are various algorithm for the production of the high speed VLSI different circuits. Among these the CORDIC algorithm [1, 5] is most popular for the designing of the high speed VLSI architecture. For the reduction of occupied space and energy consumption we design the scale free CORDIC architecture. This paper proposed a CORDIC pipelined architecture. By this architecture we compute the sine cosine function, and also we design the high pass FIR Filter by using VHDL language. The sine cosine generator and high pass FIR filter have synthesized by using typical and scale free CORDIC algorithm. These designing are simulated and tested on FPGA Virtex 4 device. These codes have synthesized using Xilinx ISim 13.1 simulator software. We also discuss about the total energy consumption, plot of output of the Filter and their analysis. Give the relative examination of the typical CORDIC algorithm and scale free CORDIC algorithm based designing. General Terms CORDIC Algorithm, Filter Designing.

Sine and Cosine Generator and FIR Filter Designing based on CORDIC Algorithm