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Design of a Three Stage Ring VCO in 0.18 µm CMOS under PVT Variations
Author(s) -
N. Ramanjaneyulu,
Donti Satyanarayana,
Khanis Satya
Publication year - 2017
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/ijca2017914932
Subject(s) - computer science , voltage controlled oscillator , cmos , stage (stratigraphy) , ring (chemistry) , electrical engineering , voltage , chemistry , engineering , paleontology , organic chemistry , biology
This paper describes the design of a 3.4 GHz three stage Ring Voltage Controlled Oscillator (VCO). In order to achieve wide tuning range at gega hertz frequencies a three stage ring oscillator based VCO is designed using differential delay cell. The linearity is achieved over a wide-tuning range from 1.5 GHz to 3.8 GHz while maintain the phase noise -116 dBc/Hz at 3.4GHz.The designed VCO is simulated using Cadence 0.18-μm CMOS process and VCO consumes 8.58 mA current and 15.4mW power from a 1.8V power supply. The designed VCO is generating a frequency of 3.4 GHz over a temperature range from 0 C to 65 C. The VCO has been found to work for all Process (Typical, Slow and Fast corners), Voltage and Temperature (PVT) conditions.

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