Design and Simulation of BIST based 4-Bit Binary Comparator based on Reversible Logic Architecture

In the present time, improvement of some fields like nanotechnology, low power design and quantum computing reversible logic circuit has emerged as a great prospect of research. With the help of using existing reversible gates a 4 bit reversible comparator based on classical logic circuit is represented. This work presents a BIST based architecture of a comparator design has a reduced number of constant inputs, garbage outputs and quantum cost. General Terms BIST, Comparator, Quantum Cost, Reversible Gate Architecture, Garbage Output.