An Efficient Hybrid Parallel Prefix Adders for Reverse Converters using QCA Technology | Zendy

N. Chandini | Zendy; B. Chinna | Zendy; Arman Jaya | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

An Efficient Hybrid Parallel Prefix Adders for Reverse Converters using QCA Technology

Author(s) -

N. Chandini,

B. Chinna,

Arman Jaya

Publication year - 2016

Publication title -

international journal of computer applications

Language(s) - English

Resource type - Journals

ISSN - 0975-8887

DOI - 10.5120/ijca2016911528

Subject(s) - computer science , adder , converters , prefix , parallel computing , arithmetic , computer architecture , computer hardware , electrical engineering , telecommunications , mathematics , linguistics , philosophy , voltage , engineering , latency (audio)

In many building blocks of microprocessors and digital signal processing chips, adders are frequently available in their critical paths. Adders can also be used for subtraction, multiplication and division. One of the important basic arithmetic operations is addition. There are several structures like Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) to perform the addition. Parallel prefix adders speed up the addition operation when compared to the other structures. Generally these adders provide less power consumption, but these consume more power when these are used in reverse converters. To reduce this high power consumption, hybrid parallel prefix adders can be used. In this paper, two structures namely, Hybrid Regular Parallel Prefix XOR/OR (HRPX) Adder and Hybrid Modular Parallel Prefix Excess-one (HMPE) Adder are discussed which uses modulo addition. Further these two adders are implemented using the Quantum dot cellular automata (QCA) technology, which reduces the delay. This entire work is done in Xilinx 13.2 tool ISE simulator.

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research