Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier

In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficiency than the multipliers involving Vedic mathematics formulae. General Terms Karatsuba algorithm, Vedic multiplier, classical multiplication.