Fault Diagnosis in Analog Integrated Circuits Using Artificial Neural Networks

One of the most important tasks in design and manufacturing of integrated circuits is the testing phase. Distinguishing between faulty and fault free ICs is a difficult task Therefore, simulations are being done for different circuits to identify fault free and faulty circuits. Analog circuits like Low pass filter, High pass filter, Band pass filter, Band reject filter, State variable filter, Tow Thomas Biquadratic filter etc. The parameters measured are the variations in node voltages & DC supply current. These parameters are specifically chosen for extracting the data, because of their ability to improve the efficiency of ANN. 1.. INTRODUCTION In today‟s semiconductor world, integration technology is improving and refining dramatically. With the continuous increase of integration densities and complexities, the problem of integrated circuit (IC) testing has become much more acute. IC testing is now no more a back-end issue, rather it has become a front-end burning issue, which needs an economic solution with reliable performance. Electronic equipments and products have become part and parcel of our daily life. Zero failure, high reliability and longevity are major business issues as well as customer expectation for the electronic goods. In many applications, accuracy and high reliability are essential and even life critical as in medical and aerospace applications. The key components of an electronic product are integrated circuits (ICs). Dramatic improvement of integration technology in IC manufacturing is rapidly leading to exceedingly complex, multimillion transistor chips. All the functionalities of an electronic system are being integrated on a single chip in less than 2 cm2 silicon area. It is known as system-on-a chip (SoC) which is the future of the IC technology. This growth is expected to continue in full force for the future years. However to make its production practical and cost effective, the semiconductor industry roadmaps identify a number of major hurdles to overcome. The key hurdle is related to test and diagnosis. Since 1990, the Semiconductor Industry Association (SIA) has been working to construct a roadmap to show the trends of research and development in integrated circuit technologies. SIA‟s prediction shows that the basic motto for the research in semiconductor technology is „„the smaller the device, the lower the cost, the higher the performance‟‟. Moore‟s Law predicts that silicon complexity quadruples every three years. The figure below shows SIA‟s projection of the number of transistors per cm2 and feature size in micrometer for complex ICs (such as microprocessor). It shows that the feature size of the transistors is decreasing exponentially whereas transistors density that can be fabricated per cm2 is increasing exponentially Fig 1.1 SIA’s Projection showing increasing number of transistors/cm 2 and decreasing feature size Within the context of such increasing integration densities and complexities, problems associated with the testing of ICs such as test generation, testing time, testing speed, testing cost, test scheduling, test access mechanism, controllability of the inputs, observability of the outputs have become much more complex and acute. The cost of testing has become a major portion of the total cost of an electronic product. It is predicted in a survey that it will soon cost more to test a transistor than to make it provided the current trend of increasing complexities are maintained.Fig.1 shows that although the costs associated with transistor manufacturing continue to shrink, testing costs are on the rise. In contemporary integrated circuits (IC), testing and test evaluation are becoming very important but very complex tasks. On one side, test efficiency and achieved reliability of IC production are of utmost importance but on the other hand, time and complexity of the test are crucial aspects from test cost point of view. Thus, the main goal of testing is to achieve desired IC reliability in the shortest possible time to satisfy customer‟s needs with appropriate time to market and profit. Many defectoriented test methods might be considered as parametric since their decision criteria are based on the analysis of analog, time continuous parameters, that is supply current signal, output current, etc. However, in defect-oriented test strategies, a meaningful threshold needs to be defined to distinguish between good and bad circuits. This is the crucial point of all thresholdbased test methods because improper setting of the pass/fail limit may essentially reduce either yield, or quality of the production. Moreover, most of the proposed defect-oriented test methods R.Srinivasa Raghavan SRM University R.Venkatraman SRM University ©2010 International Journal of Computer Applications (0975 8887) Volume 1 – No. 27 79 suffer from a poor versatility. They effectively cover a dedicated defect class only, either opens or shorts, and their use for both analog as well as digital circuits is strongly limited Fig 1.2 SIA’s Projection of Testing and Manufacturing Costs