Hardware Implementation of an Improved Resource Management Scheme for Fault Tolerant Scheduling of a Multiprocessor System

Safety-critical systems have to be fault tolerant and also meet stringent temporal constraints. Various redundancy strategies are built into such mission-critical applications to ensure the overall success of the mission. This paper implements a fault tolerant scheduling scheme on a dual processor system, wherein the redundancy is made at the task level. The system continues to function with graceful degradation under failure conditions. The redundancy management employed in the proposed scheme enhances the performance capability of the system. Based on this approach, the scheme is implemented with hardware simulation using LPC-2148 development boards. This simulation when used for implementing any practical safetycritical application can contribute to efficient utilization of computing resources and can prove to be highly cost effective as the number of processors increase.