Architectural Analysis of RSA Cryptosystem on FPGA

paper presents different architectures in FPGA based implementations of a public key crypto algorithm - RSA algorithm. A hardware-based cryptographic system is preferred as it provides - better security, integrity and is resistant to power analysis attacks (1). After the complete cryptosystem is simulated in VERILOG (8) and synthesized for specific XILINX FPGAs, the architecture of the cryptosystem is evolved by performing scheduling in the Data Flow Graph. This way there are two types of architectures realized: - one with high concurrency (which takes lesser number of clock cycles) and the other with maximum sequential operations. Subsequently the size of the key is extended and its effects on the architecture, with respect to area and power consumed, are observed. Finally trade-off analysis of the various implementations is done.