BuiltIn SelfRepair for multiple RAMs with different Redundancies in a SOC

As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.