A Novel Approach to Reduce the Gate and Subthreshold Leakage in a Conventional SRAM BitCell Structure at DeepSub Micron CMOS Technology

In the age of scaled silicon technology to improve the functional efficiency of a CMOS design, the device geometry and device parameters are constantly scaled. The major factors of the power consumption due to continuous reduction of the oxide thickness (tOX) is the gate leakage current in both the active and standby mode of the device and other is due to scaled supply voltage, the sub-threshold leakage current. This work proposes a novel approach called as the P3 SRAM Bit-Cell Scheme for the reduction of the active and standby leakage power through the gate and sub-threshold leakage reduction in the active and standby mode of the memory operation. As the gated transistor is of minimum feature size, so the area penalty is minimum in terms of a large memory and can be compromised. To the best of my knowledge, pMOS Gated-Ground and full-supply voltage body bias for pMOS transistor along with the PP SRAM bit-cell structure is used for the first time in the memory bit -cell design to reduce the power in 45nm CMOS technology at VDD = 0.7V and 0.8V. In comparison with the Conventional and PP SRAM Bit-cells, the active power is achieved for Write Data „0‟ as 89.21% , 94.38%, and for Write Data „1‟ as 89.23%, 94.45%, respectively at VDD = 0.7V. When the VDD = 0.8V, the active power is achieved for Write Data „0‟ as 9.15%, 93.63%, and for Write Data „1‟ as 91.68%, 93.59%, respectively.