Design and VLSI Implementation of a High Throughput Turbo Decoder

Turbo codes are one of the most efficient error correcting code which approaches the Shannon limit. However the major drawback of turbo codes is its high latency due to its iterative decoding process. The high throughput in turbo decoder can be achieved by parallelizing several Soft Input Soft Output(SISO) units together. In this way, multiple SISO decoders work on the same data frame at the same time. When more number of SISO decoders is connected parallel, the turbo interleaver creates a bottleneck in the system due to the contentions it introduces in accesses to memory. This delays the decoding process. In this paper, an advanced parallel interleaver called Quadratic Permutation Polynomial (QPP)interleaver is used which resolves the memory collisions introduced by parallel SISO decoders. The required area for the chip can be reduced by the help of efficient utilization of the SISO decoders. A method called Next Iteration Initialization is also used in order to reduce latency produced by a turbo decoder. The proposed Turbo decoder is expected to provide a throughput above 100Mbps. General Terms Error correction, Channel coding, MAX-LOG-MAP algorithm,